Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening

This paper describes an algorithm for curvilinear detailed routing. We sign ificantly improved the average time performance of Gao's algorithm by resol ving its bottleneck related to generation of fan-shaped forbidden regions a long a wire. We also describe a method for simultaneous wire-spreading and wire-fattening, which consists of enlarging forbidden regions generated by the detailed routing algorithm as long as there remains any space through w hich wires can pass, From the experiments me obtained the result that the a verage CPU time of the detailed routing algorithm is almost linear to the l ength of a wire. Since the curvilinear detailed routing is efficient in ter ms of space usage, the proposed algorithm is important especially for dense ly mired printed circuit boards such as pin grid array packages, ball grid array packages, and multichip modules. We can also expect improvements on t he electrical characteristics and the production yield by applying wire-spr eading and mire-fattening to them.