A low overhead design for testability and test generation technique for core-based systems-on-a-chip

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest sy stem design methodology has several advantages in terms of time-to-market a nd system cost, testing such core-based systems is difficult, mainly due to the problem of justifying test sequences at the inputs of-a core embedded deep in the circuit and propagating test responses from the core outputs. I n this paper, we first present a design for testability technique for testi ng such core-based systems. In this scheme, untestable cores are first made testable using hierarchical testability analysis techniques. If necessary, additional testability hardware is added to the cores to make them transpa rent so that they can propagate test data without information loss. This te stability and transparency technique is currently applicable to cores of th e following types: application-specific integrated circuits, application-sp ecific programmable processors, and application-specific instruction proces sors. Other core types can be made testable and transparent using tradition al techniques. The testable and transparent cores can then be integrated to gether with some system-level testability hardware to ensure justification of precomputed test sequences of each core from system primary inputs to th e core inputs and propagation of test responses from core outputs to system primary outputs. Justification and propagation of test sequences are done at the system level by extending and suitably modifying the symbolic hierar chical testability analysis method that has been successfully applied to: r egister-transfer level circuits. Since the testability analysis method is s ymbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a by-product of the testability anal;sis and insertion method without further search. The test methodology was applied to six example systems. Besides the proposed test m ethod, the two methods that are currently used in the industry were also ev aluated: I) FScan-BScan, where each core is full-scanned and system test is performed using boundary scan and 2) FScan-TBus, where each core is full-s canned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay over head, and test application time compared to FScan-BScan and FScan-TBus, wit hout any compromise in the system fault coverage.