Neuro-fuzzy architecture for CMOS implementation

In this paper, a nonconventional structure for a "fuzzy" controller is prop osed, It does not require signal division, and it produces control surfaces similar to classical fuzzy controllers. The structure combines fuzzificati on, MIN operators, normalization, and weighted sum blocks. The fuzzy archit ecture is implemented as a VLSI chip using 2-mu m n-well technology. A new fuzzification circuit, which requires only one differential pair per member ship function is proposed. Eight equally spaced membership functions are us ed in the VLSI implementation. Simple voltage MIN circuits are used for rul e selection. A modified Takagi-Sugeno approach with normalization and weigh ted sum is used in the defuzzification circuit. Weights in the defuzzifier are digitally programmable with 6-bits resolution.