Minimizing the required memory bandwidth in VLSI system realizations

In this paper, we present the problem of storage bandwidth optimization (SB O) in VLSI system realizations. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The importance and the effect of SBO is shown on realistic e xamples both in the video and asynchronous transfer-mode (ATM) domains. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. Our problem formulation leads to the optimization of a conflict (hyper) graph. For the target domain of ATM, only flat graphs without loops have to be treated, For this subproblem, a prototype tool has been impleme nted to demonstrate the feasibility of automating this important system des ign step, An automatable technique for distributing the cycle budget over d ifferent loops will be presented in a future paper.