A closed-form solution for the output signal of a CMOS inverter driving an
RLC transmission line is presented, This solution is based on the alpha pow
er law for deep submicrometer technologies, Two figures of merit are presen
ted that are useful for determining if a section of interconnect should be
modeled as either an RLC or an RC impedance. The damping factor of a lumped
RLC circuit is shown to be a useful criterion. The second useful figure of
merit considered in this paper is the ratio of the rise time of the input
signal at the driver of an interconnect line to the time of Eight of the si
gnals across the line, AS/X circuit simulations of an RLC transmission line
and a five-section RC II circuit based on a 0.25-mu m IBM CMOS technology
are used to quantify and determine the relative accuracy of an RC model, On
e primary result of this paper is evidence demonstrating that a range for t
he length of the interconnect exists for which inductance effects are promi
nent. Furthermore, it is shown that under certain conditions, inductance ef
fects are negligible despite the length of the section of interconnect.