Pausible clocking-based heterogeneous systems

This paper describes a novel communication scheme, which is guaranteed to b e free of synchronization failures, amongst multiple synchronous and asynch ronous modules operating independently, In this scheme, communication betwe en every pair of modules is done through an asynchronous first-in first-out (FIFO) channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshake signals to the local module clock is done in an unconventional way [1]-[4]-the local c lock built out of a ring oscillator is paused or stretched, if necessary, t o ensure that the handshake signal satisfies setup and hold time constraint s with respect to the local clock. In order to validate this scheme, we imp lemented a test chip in 0.5-mu m CMOS. This chip is designed as a ring, com posed of two synchronous modules, an asynchronous module, and two asynchron ous FIFO's. Each module functions as a receiver to one module and a sender to another module. Test results show that the chip functions reliably up to 456 MHz.