Logic emulation is a technique that uses dynamically reprogrammable systems
for prototyping and design verification. Using an emulator, designers can
realize designs through a software configuration process and perform real-t
ime design verification before fabricating the chip into silicon. However,
converting designs into an emulator involves the use of multiphase design t
asks, which is a very time-consuming process. Hence, shortening the time to
emulation is always the main concern for the logic-emulation design proces
s. One approach to shorten the design processing time is to replace portion
s of the design with macro cells. This paper presents a module generator fo
r logic-emulation applications, which is able to generate macro cells of ar
bitrarily complex functions described in hardware descriptive languages. Fu
rthermore, the module generator can effectively generate a multiple field-p
rogrammable gate array (FPGA) macro for large macros that cannot fit in a s
ingle FPGA chip. Experiments using the module generator for logic emulation
are reported. The results demonstrate that the module generator can effect
ively and efficiently generate complex macros from their register-transfer-
level description. In addition, the results also show that the design proce
ssing time is significantly shortened when the module generation method is
incorporated into the logic-emulation design flow.