Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

Novel techniques for power-efficient implementation of sum-of-product compu tation are presented. The proposed techniques aim at reducing the switching activity required for the successive evaluation of the partial products, i n the busses connecting the storage elements where data and coefficients ar e stored to the functional units. This is achieved through reordering the s equence of evaluation of the partial products. Heuristics based on the trav eling salesman problem are proposed to perform the reordering for different categories of algorithms, Information related to both data (dynamic) and c oefficients (static) is used to drive the reordering. Experimental results from the application of the proposed techniques on several signal-processin g algorithms have proven that significant switching activity savings can be achieved.