The method to optimize gate oxide integrity, hot carrier effect and electro-static discharge without sacrificing the performance in sub-quarter micron dual gate oxide process

In this paper, a simple method to optimize the reliability concerns in the input/output (I/O) circuits is proposed and verified. Moreover, less maskin g steps in the process can be achieved. In the process, super steep retrogr ade channel is only implemented at core transistors to have good gate oxide integrity in the I/O regions. A modified lightly doped drain (LDD) structu re formed by arsenic with phosphorus co-implant before poly re-oxidation is used to have long hot carrier lifetime. With the novel protection structur e, the I/O circuits can achieve high electro-static discharge (ESD) failure threshold.