Decentralized BIST methodology for system level interconnects

This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional arr ay of scan chains. The BIST modules are identical for all the scan chains e xcept for the programmable personalized memories. The personalized memory c ontains a scan stage type table for the test generation, response compressi on, and driver contention avoidance. It also contains a scan chain identifi cation number which serves as the seed for the generation of globally disti nct serial vectors. The proposed methodology achieves 100% coverage on stuc k-at and short faults.