An accumulator-based BIST approach for two-pattern testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In th is paper the Accumulator-Based Two-pattern generation (ABT) algorithm is pr esented, that generates an exhaustive n-bit two-pattern test within exactly 2(n) x (2(n) - 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implemen tation) or a Linear Feedback Shift Register (LFSR-based implementation). Wi th the counter-based implementation different modules, having different num ber of inputs, can be efficiently tested using the same generator. For circ uits that do not contain counters, the LFSR-based implementation can be imp lemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in t he hardware overhead. The great advantage of the presented scheme is that i t can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.