Deterministic built-in pattern generation for sequential circuits

We present a new pattern generation approach for deterministic built-in sel f testing (BIST) of sequential circuits. Our approach is based on precomput ed test sequences, and is especially suited to sequential circuits that con tain a large number of flip-flops but relatively few controllable primary i nputs. Such circuits, often encountered as embedded cores and as filters fo r digital signal processing, are difficult to test and require long test se quences. We show that statistical encoding of precomputed test sequences ca n be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal C omma codes are especially useful for test set encoding. This approach explo its recent advances in automatic test pattern generation for sequential cir cuits and, unlike other BIST schemes, does not require access to a gate-lev el model of the circuit under test. It can be easily automated and integrat ed with design automation tools. Experimental results for the ISCAS 89 benc hmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to mo derate hardware overhead.