Self-timed boundary-scan cells for multi-chip module test

This paper presents a self-timed scan-path architecture, to be used in a co nventional synchronous environment, and with basic application in digital t esting and interconnections checking in a Smart-Substrate MCM (T.A. Garcia, A.J. Acosta, J.M. Mora, J. Ramos, and J.L. Huertas, "Self-Timed Boundary-S can Cells for Multi-Chip Module Test," Proceedings of IEEE VLSI Test Sympos ium, April 1998, pp. 92-97). With this approach, the potential advantages o f self-timed asynchronous systems are explored for their practical use in a classical MCM testing application. Three different self-timed asynchronous boundary scan cells are proposed (Sense, Drive and Drive&Sense cells) that can be connected to form a self-timed scan-path. The main advantage is tha t no global test clock is needed, avoiding clock skew and synchronization f aults in test mode, and hence, a more reliable test process is achieved. Th ese cells have been designed and integrated in active substrates, building several boundary-scan configurations and being fully compatible with the AN SI/IEEE 1149.1 Standard. The experimental results, as well as their compari son with their synchronous counterparts, show the feasibility of the propos ed self-timed approach for testing interconnections in a MCM.