Structural fault testing of embedded cores using pipelining

The purpose of this paper is to develop a global design for test methodolog y for testing a core-based system in its entirety. This is achieved by intr oducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circ uitry itself. The interconnections are thoroughly tested because they are u sed to propagate test data (patterns or signatures) in the system. The syst em is modeled as a directed weighted graph in which the accessibility (of t he core input and output ports) is solved as a shortest path problem. Final ly, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The exper imental results show higher fault coverage and shorter test time.