On design validation using verification technology

Despite great advances in the area of Formal Verification during the last t en years, simulation is currently the primary means for performing design v erification. The definition of an accurate and pragmatic measure for the co verage achieved by a suite of simulation vectors and the related problem of coverage directed automatic test generation are of great importance. In th is paper we introduce a new set of metrics, called the Event Sequence Cover age Metrics (ESCMs). Our approach is based on a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test genera tion. During simulation we monitor, in addition to state and transition cov erage, whether certain control event sequences take place or not. We then c ombine formal verification techniques, using BDDs as the underlying represe ntation, with traditional ATPG and behavioral test generation techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph, or exercise an uninstantiated control event se quence.