Experience in validation of PowerPC (TM) microprocessor embedded arrays

Design validation for embedded arrays remains as a challenging problem in t oday's microprocessor design environment. Although several methods for vali dating embedded arrays have been proposed, not much has been done to charac terize the strengths and weaknesses of these methods. This paper provides a comprehensive study of various design validation approaches adopted at the Somerset PowerPC Design Center in the past, including methods from both fo rmal verification and test generation. Effectiveness of these approaches wi ll be measured based on automatic design error injection and simulation at both gate and transistor levels. Experience of using different validation a pproaches on recent PowerPC microprocessor arrays will be analyzed and disc ussed.