ARCHITECTURAL STUDY OF A BLOCK-RECURSIVE MOTION ESTIMATION ALGORITHM

The block-recursive algorithm for motion estimation is an option to cl assical methods like block-matching usually used in conventional codin g schemes based on motion compensation. The block-recursive algorithm considered in this study has been developed at IRISA in the Temis grou p. It is composed of three steps: estimation, deterministic relaxation , and quadtree region splitting. These steps are iteratively executed until convergence. To be fully exploitable, a specialized VLSI archite cture for motion estimation must satisfy the following features: real- time performance, modularity, easy external interfacing, flexibility a nd reduced internal complexity. In this paper, we analyse these differ ent features with regards to the numerous parameters of the considered block-recursive algorithm. The influence of parameters on the quality of the coding algorithm is measured through numerous simulations. Arc hitectural mechanisms required for an efficient implementation are als o presented and discussed. This study falls within the framework for d erivation of a specialized parallel architecture from the initial sequ ential algorithm specification. (C) 1997 Academic Press Limited.