An analog VLSI design for a neuron with a choice of learning rules

An analog implementation of a neuron using standard VLSI components is desc ribed. The node is capable of both delta-rule and simple error-correcting l earning. Decomposition into functional blocks allows the parts of the desig n to be easily separated and understood. The connectivity problem is eased by serially encoding inputs so that all nodes in a layer are connected to a single line carrying activations from the previous layer. Performance impl ications of the architecture are considered. The design was simulated with the Spice transistor level simulator. Schemas for interconnection of large numbers of nodes and simulations of the circuitry required are presented. R esults show that effective learning is achieved by both algorithms. Impleme ntation of multiple learning rules in a single neuron is demonstrated as an effective way of increasing flexibility in neural network hardware impleme ntations. (C) 2000 Elsevier Science B.V. All rights reserved.