Phase-locked operation of RSFQ ring oscillators

Ring oscillators are the traditional on-chip clock source for RSFQ mixed-si gnal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an AID converter or the output clock of a D/A converter. However convention al bias schemes lead to excessive drift in the frequency. Embedding the rin g oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit compri sed of a ring oscillator, a divide-by-2(20) prescaler and a resynchronizer D flipflop was fabricated using the standard 1 kA cm(-2) niobium foundry se rvice from Hypres. The circuit was stabilized using a low-frequency PLL wit h a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring os cillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscilla tor output was measured in open- and closed-loop configurations. Compared t o the open-loop phase noise spectrum the closed-loop spectrum showed a decr ease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the d ivided-down carrier frequency of 4.1 kHz. This agreed with the classical ph ase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz os cillator used as the reference in the PLL.