Full-scale integration of superconductor electronics for petaflops computing

Ultralow-power and ultrahigh-speed single-flux-quantum electronics is an en abling technology solution for near-term petaflops computing. The proposed hybrid technology multithreaded (HTMT) petaflops-scale computer architectur e includes computational modules operating at 100 GHz and an I/O throughput of 32 Pbits s(-1). In this frequency regime, on-chip interconnect mimics t he system interconnect problem. On-chip latency can be minimized with incre ased gate density by using more levels of metal and smaller line pitch. Thi s may be even more important than increasing the maximum clock rate by usin g smaller junctions and higher critical current density. Superconductor ICs at an integration level of 100k gates cm(-2) are proposed for the processo rs, first-level cache and interprocessor network. Petaflops capacity will r equire a compact, optimized system-level packaging strategy to achieve the necessary computational density and interconnect bandwidth. Modular packagi ng and automated circuit testing are required to minimize manufacturing cos ts. We focus on the critical technology challenges that exist for the IC fo undry, packaging and the I/O data link and present technology roadmaps to a chieve the HTMT requirements.