Branch prediction, instruction-window size, and cache size: Performance trade-offs and simulation techniques

Design parameters interact In complex ways in modern processors, especially because out-of-order issue and decoupling buffers allow latencies to be ov erlapped. Trade-offs among instruction-window size, branch-prediction accur acy, and instruction- and data-cache size can change as these parameters mo ve through different domains. For example, modeling unrealistic caches can under- or overstate the benefits of better prediction or a larger instructi on window. Avoiding such pitfalls requires understanding how all these para meters interact. Because such methodological mistakes are common, this pape r provides a comprehensive set of SimpleScalar simulation results from SPEC int95 programs, showing the interactions among these major structures. In a ddition to presenting this database of simulation results, major mechanisms driving the observed trade-offs are described. The paper also considers ap propriate simulation techniques when sampling full-length runs with the SPE C reference inputs. In particular, the results show that branch mispredicti ons limit the benefits of larger instruction windows, that better branch pr ediction and better instruction cache behavior have synergistic effects. an d that the benefits of larger instruction windows and larger data caches tr ade off and have overlapping effects. In addition, simulations of only 50 m illion instructions can yield representative results if these short windows are carefully selected.