Low power flip-flop design based on PAL-2N structure

Adiabatic or energy-recovery logic has gained much attention recently in th e development of low-power digital logic. The previously proposed adiabatic logic families have focused mainly on combination logic. In this paper, we extend this principle to the design of flip-flops. SR and JK Aip-flop desi gns based on the pass-transistor adiabatic logic with NMOS pull-down config uration (PAL-2N) are presented. Based on the simulation results, these adia batic flip-flops outperform their CMOS counterparts in terms of power consu mption. The operation of a 4-bit binary counter developed using the propose d JK flip-flop has also been simulated and verified. (C) 1999 Elsevier Scie nce Ltd. All rights reserved.