In this paper, we describe the design and development of the central trigge
r system (CDL) for the BELLE detector at the KEK B-factory. The GDL consist
s of four types of single width 6U VME modules (ITD, FTD, PSNM and TMD) whi
ch are designed using the programmable logic techniques of Xilinx FPGA and
CPLD. Individual and combined performance tests of these modules are done a
nd it is confirmed that the GDL functions as expected. (C) 1999 Elsevier Sc
ience B.V. All rights reserved.