A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-mu m CMOS

This paper describes the design of a two-step analog-to-digital converter ( ADC), By using techniques such as improved switching and offset-compensated amplifiers, the high-speed two-step architecture can be expanded toward hi gh resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, ata sample rate of 25 MSample/s, The ADC is realized in a 0.35-mu m mainstream CMOS process without options such as double poly,It measures 0.66 mm(2) and dissipates 195 mW from a 3.3-V power supply.