Threshold voltage shift in 0.1 mu m self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs

Bias-temperature stress examinations of self-aligned 0.1 mu m length gate G aAs MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lower d oping concentration, the increase in threshold voltage in FETs was faster a nd a 100 mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200 degrees C. The recovery of the per formance under reverse-biased stresses was observed. The degradation is rel eased by increasing Si doping concentration and thus we obtained the predic tion of a median life exceeding 10(6) h at 100 degrees C by setting the Si dose of 4 x 10(13) cm(-2), which is as high as it can be set without causin g serious reduction of breakdown voltage. (C) 1999 Elsevier Science Ltd. Al l rights reserved.