Investigation into socketed CDM (SDM) tester parasitics

The ESD Association standards working group 5.3.2 is analyzing the procedur e and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Ou r final goal is to define an SDM tester specification that will guarantee t est result reproducibility across different test equipment. This paper inve stigates the effect of tester background parasitics on the discharge curren t waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester paras itics determine the stress applied to the DUT. This directly impacts the SD M failure threshold voltage levels and may lead to miscorrelation and non-r eproducibility of test results across different SDM test systems. This pape r empirically determines the relative contributions of the various tester p arasitics to the total stress applied to the DUT. Our investigations indica te that the tester provides a 10-20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test sys tems built by different manufacturers is unlikely without completely duplic ating a particular tester. (C) 1999 Elsevier Science Ltd. All rights reserv ed.