We have investigated different comparators for Flash and Sigma-Delta high t
emperature superconducting ADCs designed using three-layer HTS tri-crystal
junction integrated circuit technology with spread of the junction critical
currents less than 10% and features size 0.6 mu m. Using the theoretical e
stimations for the bit error rate in RSFQ circuit under the restrictions of
the given technology, we have estimated working temperature as T = 62 K. A
t this temperature, the circuits were optimized in order to achieve maximum
performance of the related ADCs in terms of input bandwidth, resolution an
d operating margins. For design purposes, a novel method was developed for
inductance calculation with 3D magnetic field distribution in multilayer su
perconducting technology and extraction of the inductance matrix of the equ
ivalent circuit. (C) 1999 Elsevier Science B.V. All rights reserved.