Clock multiplier using digital CMOS standard cells for high-speed digital communication systems

The authors propose and evaluate the performance of a 2(N) times clock mult iplier that controls memory components for high-speed data communications. To improve the reliability of the circuit, a symmetric circuit structure is used, while to verify circuit operation by means of a simple method, an MW estimator is found from simulation data. The proposed circuit can provide clock rates, which are usually required in the multiple phase shift keying (MPSK) or multiple quadrature amplitude modulation (MQAM) modulation scheme s, of 2 to 2(N) times that of the input clock.