Very high density trench gate power MOSFET using simplified four-mask process

A new and simplified process for fabricating a high density n-channel trenc h gate power MOSFET using four mask layers and a sidewall spacer technique is proposed. Use of this process has enabled a remarkably increased high de nsity (100Mcell/in(2)) trench MOSFET with a cell pitch of 2.5 mu m to be re alised. Furthermore, the p-base, n(+)-source, and trench gale regions were formed by the same mask layer, which made it possible to reduce the number of processing steps. The fabricated device had a low specific on-resistance of 0.7 m Omega cm(2) with a breakdown voltage of 46V.