Diagnosing delay faults in combinational circuits under the ambiguous delay model

In our previous paper [9] we presented a path-tracing method of multiple ga te delay fault diagnosis in combinational circuits. In this paper, we propo se an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of I Cs. For the effectiveness of the current method, we propose a timed 8-value d simulation and some new diagnostic rules. Furthermore, we introduce a pre paratory process that speeds up diagnosis. Also, at the end of diagnosis, a dditional information from the results of the preparatory process makes it possible to distinguish between non-existent faults and undiagnosed faults.