VLSI floating resistors for neural type cell arrays

Two novel CMOS circuit designs implementing floating resistors are introduc ed, using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear res istors and cascode current mirrors in the second configuration. Linearity i s achieved through nonlinearity cancellation via current mirrors over an ap plied range of +/-5V. PSpice simulation results using parameters of MOSIS t ransistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays.