Analog dendro-dendritic arrays with digital on-chip learning

A design of arrays of CMOS analog Dendro-dendritic Artificial Neural Networ k (DANN) chips with on-chip digital learning is described. The building blo cks, namely, the neuron unit and the adaptive synapse, are employed to cons truct several architecutures. One design comprises a reconfigurable fully-c onnected array chip integrating 50-neurons. A second array chip design inte grates (9 x 9 = 81) neuron units and 825 locally-connected reconfigurable w eights. In all cases, a connection is realized as a single (nonlinear) tran sistor with adaptive digital circuitry. The chip is designed and fabricated in 6.8 mm x 4.6 mm chip size using 2 mu m CMOS technology. As an example o f an application of the fabricated dendro-dendritic neural chips, real-time experiments are described in which the chips are used as a parallel digita l coprocessor to demonstrate their applicability as pattern associators. Th ese experiments entail learning an arbitrary binary image in about 10 ns wi th guaranteed learning capability. The stored image can subsequently be ret rieved by images distorted by binary-noise in the order of 100 ns. The powe r dissipation of these chips in steady state is less than 5 mW using 0/5 V power supply.