Fully planarized process integration and its effects on the process marginfor 0.15-micron DRAM technology

A current DRAM integration with respect to interconnection and metallizatio n has a problem of small process window margin due to large topology differ ence between cell array and peripheral area. In this paper, a fully planari zed DRAM process integration has been developed. A high aspect ratio metal contact was successfully formed with aspect ratio of 9.2:1. TMP sputter dep osited Ti and TiN thin films were applied for ohmic and barrier material. C ontact resistances were 300 ohm/contact in M/n(+) contact, and 600 ohm/cont act in M/p(+) contact, respectively. Contact leakage currents were less tha n few fA/contact for both M/n(+) and M/p(+) contacts. A DOF margin of metal pattern was dramatically increased as a result of full planarization proce ss.