A 3.3 V 128 Mb NAND type flash memory achieves 2.3 MB/s with an incremental
step pulse programming (ISPP) scheme and a 24 MB/s read through-put with i
nterleaved data paths. In addition, in order to reduce the programming inte
rference for the program inhibited cell, a semilocal, self-boosting (SLSB)
of program inhibit voltages scheme is proposed. The device is fabricated wi
th a 0.275 mu m CMOS process on a 134 mm(2) die.