A 3.3-V 4-Mb nonvolatile ferroelectric RAM : Novel design techniques immune to instable cell capacitor

This work presents, for the first time, a 4 mega-bits FRAM with novel desig n techniques which are deviced to achieve a stable FRAM cell operation; 1) open bitline cell array, 2) selectively-driven double-pulsed plate read/wri te-back scheme, and 3) complementary data preset reference circuitry and re laxation/fatigue/imprint-free reference voltage generator. The prototype de vice incorporating these circuit schemes shows 75 ns access time, 21 mA act ive current at 3.3 V, 25 degrees C and 110 ns cycle. It measures 116 mm(2) using 0.6 mu m CMOS technology.