A 1.6 gbyte/s 16-bank 72 Mb DRAM with block-decoded sub-YSEL driver

A 16-bank 72 Mb DRAM which adopted a merged bank architecture (MBA) and a b lock-decoded column accessing scheme to reduce column operating power and c olumn access time, was fabricated under the technology of triple metals, tr iple wells and 2.5 V, 0.25 mu m CMOS process. The simulation has shown a po wer reduction by 50% or above compared to other schemes and the internal da ta access time (t(Dac)) was measured to be 5.2 ns on the silicon under the worst conditions.