This paper presents a 9 mW frequency synthesizer with a dual-modulus (divid
ed by 64/65 divided by 128/129) prescaler that operates up to 1.2 GHz using
Samsung's 0.5 mu m BiCMOS technology. Ih this paper, a new architecture is
proposed to improve the dead-zone characteristic in PFD (Phase Frequency D
etector) and to reduce the reference spurious tones. Also, preamplier and E
CL (Emitter Coupled Logic) blocks are optimized to achieve low power design
, with tradeoffs between the maximum operating frequency and the current co
msumption. As a result, the phase noise of -62.53 dBc/Hz at a 500 Hz offset
and the reference spurs of -86.17 dBc at a 30 kHz offset were achieved. Th
e proposed frequency synthesizer consumes about 3.0 mA in the power supply
range of 2.7 V similar to 5.5 V even though ECL circuits were used.