A 2 GHz CMOS downconverter with robust image rejection performance againstthe process variations

The proliferation of mobile communication systems such as cellular, cordles s phone, and PCS has brought about a great demand for a low-cost, low-power , small form-factor transceiver. In order 60 satisfy these requirements, re cent researches are focused toward the development of a monolithic transcei ver using advanced CMOS technologies. In this paper, a monolithic 2 GHz CMO S image rejection downconverter is described. The proposed downconverter is fully integrated with six mixers and four on-chip 90 degrees phase shifter s. The main features of this downconverter are to provide improved linearit y and robust image rejection performance against the process and temperatur e variations. Thus the image rejection ratio depends on only the relative m atching property of passive IC components. From the simulations with 0.65 m u m CMOS parameters, the power consumption of the proposed downconverter is 150 mW. And this downconverter suppresses the image signal by more than 50 dB even for the case of RC product variations of up to +/- 50 %. And the p roposed mixer topology improves IP3 by more than 2 dBm, compared with a con ventional Gilbert cell mixer.