A low-power PLL-based clock generator with 1 MHz similar to 152 MHz of lock range

In this paper, we introduce a low power PLL-based clock generator for porta ble communication systems. This PLL is designed using 0.75 mu m CMOS techno logy with 1.5 V supply voltage. Particularly the PLL requires no additional external components. All the components of the PLL-based clock generator, such as PFD (Phase-Frequency Detector), charge-pump, VCO (Voltage Controlle d Oscillator) and divider chain, are proposed with a new circuit technique for low voltage applications. Power consumption of the PLL is less than 0.8 mW at 1.5 V supply and the internal clock frequency range of the PLL is fr om I MHz up to 152 MHz. In order to generate various output clock frequenci es, a divider chain with 5-stage asynchronous counter is used at the input and output of the PLL. To verify the lock-in properties of the PLL, a HSPIC E simulation was performed. The peak-to-peak jitter of the PLL is less than 130 ps at 152 MHz.