A high speed VLSI architecture of adaptive equalizer and viterbi decoder for EPR-IV magnetic disk read channel

A VLSI architecture of adaptive equalizer and viterbi decoder for EPR-IV ma gnetic disk read channel is described. The 8-tap adaptive equalizer with 3- stage pipeline architecture uses a sign-LMS algorithm as the coefficient ad aptation algorithm. Novel features of the 3-stage pipelined adaptive equali zer include a new parallel saturated arithmetic circuit which can reduce th e number of pipeline stage. The viterbi decoder consists of ACS module with module comparison scheme, path memory, minimum detection unit to handle no n-convergent condition, and output selection module. The processor is desig ned using 0.35 mu m CMOS technology and consists of about 57,500 transistor s and dissipates about 0.65 watts at 3.3 V supply and operates up to 300 Mb ps.