VLSI design for high-speed LZ-based data compression

A simple real-time parallel architecture for CMOS VLSI implementation of a Ziv-Lempel data compression system is presented. This encoding system emplo ys a linear systolic allay to find concurrently the matches between each in put data character and its corresponding dictionary, and can easily achieve ideal compression ratio by cascading the chips of the encoding cell. A new encoding architecture is proposed to improve the encoding speed and reduce hardware complexity for the encoding cells. In addition, the number of mem ory accesses is reduced to save power consumption for high-speed applicatio ns. The encoder codes one character (more than eight bits) per encoding cyc le. The clock rate by Verilog simulator can be constrained below 15ns using the Compass standard cell library for the 0.6 mu m CMOS process.