A hardware implementation of the mechanism of multiprocessing

Citation
M. Tomasevic et al., A hardware implementation of the mechanism of multiprocessing, MICROPR MIC, 23(8-9), 1999, pp. 471-479
Citations number
9
Categorie Soggetti
Computer Science & Engineering
Journal title
MICROPROCESSORS AND MICROSYSTEMS
ISSN journal
01419331 → ACNP
Volume
23
Issue
8-9
Year of publication
1999
Pages
471 - 479
Database
ISI
SICI code
0141-9331(199912)23:8-9<471:AHIOTM>2.0.ZU;2-J
Abstract
The mechanism of multiprocessing (MMP) has been developed and implemented a s an enhancement of a standard operating system (OS ES) to support efficien t execution of fine-grained parallel activities. The MMP mechanism is prese nted through the description of its primitives, associated data structures and its interface with the OS ES. Further efficiency enhancement of the MMP mechanism has been achieved by the hardware implementation of the MMP prim itives in the specially designed processor, named the MMP processor. The de tails of its architecture and organisation are given in the paper. Special emphasis is put on the design of the efficient pipelined control, which res ulted from the precise timing analysis of the considered design choices. (C ) 1999 Elsevier Science Ltd. All rights reserved.