IC test structures for multilayer interconnect stress determination

A nem method for measuring strain in multilayer integrated circuit (IC) int erconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interc onnect stress in a standard dual-metal-layer CMOS process. Strain measureme nts are shown to be consistent for an array of similar test structures. Str ess values, calculated from constitutive relations, are in good agreement w ith published results.