A new five-parameter MOS transistor mismatch model

Citation
T. Serrano-gotarredona et B. Linares-barranco, A new five-parameter MOS transistor mismatch model, IEEE ELEC D, 21(1), 2000, pp. 37-39
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE ELECTRON DEVICE LETTERS
ISSN journal
07413106 → ACNP
Volume
21
Issue
1
Year of publication
2000
Pages
37 - 39
Database
ISI
SICI code
0741-3106(200001)21:1<37:ANFMTM>2.0.ZU;2-T
Abstract
A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and satur ation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatc h ae into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transis tors.