Power optimization of variable-voltage core-based systems

The growing class of portable systems, such as personal computing and commu nication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and desig n reuse, The energy efficiency of systems-on-a-chip (SOC) could be much imp roved if one were to vary the supply voltage dynamically at run time. We de velop the design methodology for the low-power core-based real-time SOC bas ed on dynamically variable voltage hardware. The key challenge is to develo p effective scheduling techniques that treat voltage as a variable to be de termined, in addition to the conventional task scheduling and allocation. O ur synthesis technique also addresses the selection of the processor core a nd the determination of the instruction and data cache size and configurati on so as to fully exploit dynamically variable voltage hardware, which resu lts in significantly lower power consumption for a set of target applicatio ns than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close t o optimal ones for many test cases. The effectiveness of the approach is de monstrated on a variety of modern industrial-strength multimedia and commun ication applications.