Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic i nterface circuit for a group of low-power adiabatic logic families with a s imilar clocking scheme. The circuit provides interfacing between several re cently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to cl ock overlap. With the proposed interface circuit, both adiabatic and CMOS l ogic circuits are able to co-exist on a single chip: taking advantage of th e strengths of each approach in the design of low power systems.