Implementation of a high speed frequency synthesizer employing a dual input phase accumulator

We present a new PLL based frequency synthesizer, in which we have replaced the conventional phase frequency detector and the dividers (programmable c ounters) with a sequential dual input phase accumulator (DIPA), consisting of a digital circuit employing adders, registers and a ladder. The main fea ture of the DIPA is that the two input frequencies are not required to be n ormalized (divided down) to the step frequency of the synthesizer. Instead, the two different high frequencies, that is the reference and the output f requency of the synthesizer, an applied directly. The DIPA samples and norm alizes their phases at very high rates, calculates their phase difference, producing an output that consists of a de component proportional to the pha se difference and harmonics of the two input high frequencies. These harmon ics are high frequencies and can easily be rejected by a wide bandwidth fil ter of the loop, without affecting the high convergence speed of the loop. Moreover, these harmonics do not generate spurs near the output frequency. The resolution of the DIPA based synthesizer depends only on the length of the digital word of the DIPA, and its convergence speed depends on the lowe r of the two input frequencies. The output of the DIPA is a linear function of the phase difference of the two input frequencies and its dynamic range exceeds the limit of +/- 2 pi that governs the conventional phase detector s. Thus, the proposed frequency synthesizer based on the DIPA has low phase noise, no spurs nearby the output frequency, high resolution and fast conv ergence rate. Additionally, the output frequency can be digitally modulated under the control of the closed loop, either by phase or frequency modulat ion.