Synthesis for testability of highly complex controllers by functional redundancy removal

This paper presents a testable synthesis methodology applicable to any top- down design method based on hardware;description-language descriptions, or graphical representations. The methodology is targeted on control-dominated applications and it is based on the identification and removal of a new cl ass of redundant faults, called functionally redundant faults. The formal r elation between functionally redundant faults and sequentially redundant fa ults is introduced. Moreover, the relation between functionally redundant f aults and logic synthesis algorithms based on local don't cares is shown. F unctionally redundant faults are identified and removed by comparing the im plemented synchronous sequential circuit, which can be technology dependent , to its specification. The specification can be a single finite state mach ine (FSM), a set of interacting FSMs, or a hierarchical FSM that allows the description of highly complex controllers. The proposed methodology produc es testable circuits, with area reduction, still mapped on the same technol ogy library, and it manages circuits which cannot be handled by other metho ds presented in the literature.