A buffer-oriented methodology for microarchitecture validation

We propose a methodology for validating microarchitecture specifications. W e view microarchitecture features as specific operations on entries of vari ous buffers in the processor. Our validation approach is to determine the f unctionality of a buffer type, model its operations at the microarchitectur e level using abstract finite state machine (FSM) models, and rigorously ge nerate instruction sequences that systematically exercise the model of each instance of that buffer type. A high-level test sequence is derived based on the abstract FSM model using FSM testing techniques, and then translated to a test program that exercises the functionality of each buffer entry. T his methodology is applied to the microarchitecture specifications of the P owerPC 604. The effectiveness of the sequences generated using our methodol ogy is compared with that of some real and randomly-generated programs. Sim ulation results show that all targeted FSM transitions are covered by our s equences with at least 1000 x and 3 x fewer instructions than real and rand omly-generated programs, respectively.