Formal value-range and variable testability techniques for high-level design-for-testability

This research applies formal dataflow analysis and techniques to high-level DFT. Our proposed approach improves testability of the behavioral-level ci rcuit description (such as in VHDL) based on propagation of the value range s of variables through the circuit's Control-Data Flow Graph (CDFG). The re sulting testable circuit is accomplished via controllability and observabil ity computations from these value ranges and insertion of appropriate testa bility enhancements, while keeping the design area-performance overhead to a minimum.